`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   21:11:04 05/31/2015
// Design Name:   MemoriaInstrucciones
// Module Name:   D:/Libraries/Documents/Ingenieria en computacion/Arquitectura Computadoras/TrabajoFinalArquitectura/trunk/Final-Mips/TestMemInst.v
// Project Name:  Final-Mips
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: MemoriaInstrucciones
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module TestMemInst;

	// Inputs
	reg clk;
	reg [31:0] InstAddr;

	// Outputs
	wire [31:0] Inst;

	// Instantiate the Unit Under Test (UUT)
	MemoriaInstrucciones uut (
		.clk(clk), 
		.InstAddr(InstAddr), 
		.Inst(Inst)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		InstAddr = 0;

		// Wait 100 ns for global reset to finish
		#100;
      InstAddr = 1;  
		#100;
      InstAddr = 2;  
		#100;
      InstAddr = 3;  
		//Ahi podes leer la instruccion que sigue
		#100;
      InstAddr = 4;  
		#100;
      InstAddr = 5;  					//----------------------------------//
		#100;									//**** LAS INST VAN DE 4 EN 4 ******//
      InstAddr = 6;						//----------------------------------//
		#100;
      InstAddr = 7;  
		//Ahi lees la otra
		#100;
      InstAddr = 8;  
		

	end
//Hacemos andar el clock
always begin
#1; clk = ~clk;  
end

endmodule

